This invention relates to the field of forming electrical connections to integrated circuit devices. More particularly, this invention relates to forming an extremely large number of electrical connections to an integrated circuit using an inverted interface integrated circuit.
As important as manufacturing an integrated circuit is the ability to apply electronic signals to and receive electronic signals from the integrated circuit. Ordinarily, an integrated circuit die is configured to have relatively large exposed metal areas, known as bonding pads, through which this electrical interface can be conducted. Often these metal areas are formed of aluminum or an aluminum alloy, which can for example 5 mils, square.
Several well known techniques are commercially used to realize such electrical interface. One such well known technique is conventionally called wire bonding. The completed die is mounted to a lead frame which is integral to the package, such as a dual-in-line package (DIP), pin grid array package (PGA), or other packages equally well known. The package includes individual pins or other electrical contact devices that are configured for ready coupling to an external circuit or circuit board through soldering, socketing or other well known means. Electrical contact is made between the bonding pads and the lead frame by attaching a thin wire between these contacts. The wire is attached to the bonding pads and the lead frame by heating or ultrasonically welding the wire to the pads. Unfortunately, the bonding wire introduces impedance into the path of an electric signal due to its thinness and length. The bonding wire acts as an inductor. This impedance operates to add noise to the signal, thereby decreasing the overall operating efficiency of a system including bonding wires. Further, because of the physical requirements of the wire and the potential for undesired contact between adjacent wires, the spacing requirements are restrictive. The bonding pads are positioned near the edges of the die to allow a shortest path for the bonding wire. The bonding wire can also act as an antenna.
Another well known technique is commonly known as flip chip bonding. According to flip chip bonding, a substrate such as a printed circuit board includes electrically conductive lands that are formed into a mirror image of the bonding pads on an integrated circuit. Generally, the bonding pads are treated with a layer of solder. The integrated circuit and the substrate are mounted in a face-to-face relation to one another and the solder is melted with heat to join the bonding pads and to the corresponding land. In this way, the bonding pads and the lands necessarily provide electrical contact from the integrated circuit to the substrate. Unfortunately, electrical interconnection between two integrated circuits on a printed circuit board, each die using flip chip bonding, requires signal traces along the substrate. These traces, such as on a printed circuit board, introduce impedance into the path of the electric signals and operate to slow the transmission of the signals, thereby decreasing the overall operating efficiency of such a system.
Others have proposed chip to chip bonding techniques. For example, U.S. Pat. No. 5,399,898 to Rostoker discloses a multi-chip semiconductor arrangement using flip chip dies. Rostoker teaches arrangements using double sided flip chips which have raised bumps on both sides and single sided flip chips which have raised bumps on one side. The double sided flip chips are mounted on the substrate and the single sided flip chips bridge the gap between the double sided flip chips with minimal overlap. The Rostoker invention suffers from the several difficulties in implementation. For example, an upper integrated circuit must be mounted as a bridge between two integrated circuit dice. This requires such an assembly to consume considerable surface area on a substrate such as a printed circuit board, or requires an atypically large integrated circuit package to contain such an assembly. In addition, the upper integrated circuit must be manufactured using complex processing techniques that form electrically conductive vias through the body of that integrated circuit. Such techniques are complex and thus expensive to perform. Electrical connection to this assembly is made to the back of the upper integrated circuit using for example conventional wire bonding techniques.
Still others have proposed techniques for reducing the volume and thus surface area consumed by multiple integrated circuit devices. One such technique is taught in U.S. Pat. No. 5,491,612 to Nicewarner, Jr. This technique is not concerned with the number of interconnections between integrated circuits but rather the volume of space consumed by plural integrated circuits. Nicewarner teaches a three dimensional modular assembly of integrated circuits. The chips are mounted back to back and are mounted on both sides of the primary substrate and between each of the two secondary substrates and the primary substrate. Because of the design, the array of chips between the primary substrate and the first secondary substrate must mirror the array of chips between the primary substrate and the second secondary substrate.
Yet others have proposed stacking integrated circuits one on top of another. Such techniques include forming interconnections along the sides of the stack. Heat dissipation from an integrated circuit within the stack can become a problem.
An emerging technology surrounds semiconductor micromachines that are used for forming displays. A device that can be used for such a display is disclosed in U.S. Pat. No. 5,311,360 which is incorporated in its entirety herein by reference.
According to the teachings of the ""360 patent, a diffraction grating is formed of a multiple mirrored-ribbon structure such as shown in FIG. 1. A pattern of a plurality of deformable ribbon structures 100 are formed in a spaced relationship over a substrate 102. Both the ribbons and the substrate between the ribbons are coated with a light reflective material 104 such as an aluminum film. The height difference that is designed between the surface of the reflective material 104 on the ribbons 100 and those on the substrate 102 is xcex/2 when the ribbons are in a relaxed, up state. If light at a wavelength xcex impinges on this structure perpendicularly to the surface of the substrate 102, the reflected light from the surface of the ribbons 100 will be in phase with the reflected light from the substrate 102. This is because the light which strikes the substrate travels xcex/2 further than the light striking the ribbons and then returns xcex/2, for a total of one complete wavelength xcex. Thus, the structure appears as a flat mirror when a beam of light having a wavelength of xcex impinges thereon.
By applying appropriate voltages to the ribbons 100 and the substrate 102, the ribbons 100 can be made to bend toward and contact the substrate 102 as shown in FIG. 2. The thickness of the ribbons is designed to be xcex/4. If light at a wavelength xcex impinges on this structure perpendicularly to the surface of the substrate 102, the reflected light from the surface of the ribbons 100 will be completely out of phase with the reflected light from the substrate 102. This will cause interference between the light from the ribbons and light from the substrate and thus, the structure will diffract the light. Because of the diffraction, the reflected light will come from the surface of the structure at an angle "THgr" from perpendicular.
It will become apparent to one of ordinary skill in the art after studying the teachings of the ""360 patent that the structure shown in FIG. 1 can be used to represent a single pixel of a display. A typical display can contain 1024xc3x971280 pixels arranged in an array of rows and columns. A semiconductor device using pixels such as shown in FIG. 1 and having 1024xc3x971280 pixels can have an array that is approximately 1 inch by 1.3 in extent. Such a device will likely require at least 2310 I/O structures (1024+1280+6). The additional 6 I/O pins are for specialized biasing. Using conventional wire bonding bond pad structures, the surface area necessary for making connection to such a device can exceed the active display area by several times. Because the cost to manufacture the device is primarily born by the active display area, such an expense of surface, area is excessive and undesirable. To solve this problem, it is undesirable to manufacture driver structures on the same semiconductor substrate as the active display area. This is due to two primary reasons. First, the cost to manufacture the devices in the active display area is greater than to manufacture electronic circuit components for making drivers using conventional well known techniques. Second, the processing steps are not the same to manufacture the active display area as for electronic circuit components. Thus, a processing specification for such a device would be extremely complex. This would tend to further reduce the yield of such a structure and thereby further increase the cost. For these reasons, it is preferred that the drive electronics be placed in a separate integrated circuit.
Interconnections to such a device could not require the electrically conductive vias nor the bridging technique taught by Rostoker. Further, such an interconnecting structure could not function using a stacked arrangement because light would not be able to impinge onto the surface of the active display area.
What is needed is a method of and apparatus for providing electrical interconnections directly from one integrated circuit to another.
What is also needed is a method of and an apparatus for providing electrical interconnections to an integrated circuit with extremely high I/O requirements.
What is further needed is a method of and an apparatus for providing electrical interconnections to an integrated circuit without obscuring the surface of the integrated circuit.
A method of and an apparatus for electrically interconnecting two integrated circuits devices includes mounting the two devices face to face. A first device is mounted for example to a substrate or lead frame. The first device includes a plurality of electrical/physical mounting structures preferably positioned along one edge. The mounting structures provide both electrical interconnection and physical mounting. A second device includes a corresponding plurality of mounting structures configured as a mirror image of the mounting structures on the first device. The mounting structures on the second device are also positioned along one of its edges so that once the mounting structures are brought together in a face to face relationship, the second device cantilevers off the edge of the first device. Under certain circumstances, a dummy block can be mounted to the substrate adjacent to the first device to act as a strut or support for the second device. Under certain other circumstances, an epoxy potting compound can be used to provide structural support. The mounting structures can be positioned sufficiently close to one another that surface area consumed for I/O is minimized. Another set of electrical interconnect structures can be formed on the surface of the second device on the edge opposite the mounting structures. Electrical connection can be formed to these electrical interconnect structures using conventional techniques such as tape automated bonding (TAB) or flex connections.